The Chipfilm™ technology
In the Chipfilm™ technology the chip thickness is defined by forming a buried cavity beneath the wafer surface within the chip areas.
For this purpose p-doped areas are patterned on the wafers during this preprocess that match the size of the chips to be processed. The following anodic etching process using a HF/isopropanol etching solution creates coarse and fine porous silicon layers in a two-phase etching process while n-doped areas are not affected by the etching solution. During the following (subsequent) annealing cavities matching the chip size are created from the coarse porous silicon.
The fine porous etched silicon contains the structural information of the silicon crystal enabling the growth of silicon in the requested epitaxial chip thickness and doping. The thus preprocessed Chipfilm™ substrate wafers can subsequently pass through the CMOS process without alterations opposed to a process on standard wafers, since the buried cavities practically leave the characteristics unchanged.