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New Ultrathin Chip Fabrication Process Presented at IEDM 2010 in San Francisco

December 06 - 08, 2010

During the IEEE International Electron Devices Meeting in San Francisco, scientists of renowned corporations, such as IBM, Intel, Samsung, and TSMC, presented the latest developments and leading researchers from academia demonstrated their recent findings.

Process Window for Ultrathin Chips
The team around Prof. Joachim Burghartz at IMS CHIPS presented an improved version of their Chipfilm™ technology introduced in an IEDM 2006 Late News paper four years ago, which according to them now features a manufacturable process technology.

E. A. Angelopoulos (IMS CHIPS):
"Ultra-Thin Chip Technology for System-in-Foil Applications"
E. A. Angelopoulos, M. Zimmermann, W. Appel, S. Endler, S. Ferwana, C. Harendt, T. Hoang, A. Prümm, J. N. Burghartz

Silicon Stencil Mask Technology leads to Transistor Record
Researchers from IMS CHIPS and from the Max Planck Institute (MPI) for Solid-State Research in Stuttgart have joined in an effort to demonstrate the smallest and fastest organic thin-film transistor ever built in a manufacturable fabrication process. The group of Dr. Hagen Klauk at MPI is an international leader in research and development of organic thin-film transistor (OTFT) technology with a particular focus on low-voltage (<5 V) operation.

F. Ante (Max Planck Institute for Solid State Research):
"Submicron Low-Voltage Organic Transistors and Circuits Enabled by High-Resolution Silicon Stencil Masks"
F. Ante,(a) F. Letzkus,(b) J. Butschke,(b) U. Zschieschang,(a) K. Kern,(a,c) J. N. Burghartz,(b) and H. Klauk(a)

a) Max Planck Institute for Solid State Research, Stuttgart

b) Institut für Mikroelektronik (IMS CHIPS), Stuttgart, Germany
c) Ecole Polytechnique Fédérale de Lausanne,Switzerland

For further information, please refer to
Chipfilm™ Process ready for the fabs
Silicon Stencil Mask Technology leads to Transistor Record

Location: Hilton San Francisco, Union Square, San Francisco, CA