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Chip-Film Patch cover story in IEEE journal “Transactions on Components, Packaging, and Manufacturing Technology”

July 23, 2018

The IMS CHIPS-developed adaptive layout process for silicon chips-in-foil systems is the front page story of the renowned IEEE journal “Transactions on Components, Packaging, and Manufacturing Technology” in its latest May/June 2018 edition. The scientists at IMS CHIPS offer the journal´s readers an inside into the “Adaptive Layout Technique for Micro Hybrid Integration of Chip-Film Patch”.

Chip-Film Patch (CFP) is a process developed at Institut für Mikroelektronik Stuttgart that enables the joint embedding of extremely thin micro components into a flexible bendable film laminate and subsequent wiring as hybrid micro circuit. One part of the CFP technology is the recently at IMS CHIPS developed adaptive layout technique allowing for individually positioned thin micro components to be connected to an already positioned component at a later date by creating an adaptive conductor path layout. This is realized using a laser direct writer. In conventional packaging techniques the components have to precisely be inserted into a previously created conductor path layout which poses particularly high demands on the handling technique when the components are extremely thin. Using the adaptive layout process the mounting technique can be simplified significantly and, thus, will from now on allow for a cost-efficient production of hybrid systems-in-foil.


Cover page "IEEE Journals Transactions on Components, Packaging, and Manufacturing Technology"