Workshop Chip Design Management for Users and Customers
July 08, 2019
The aim of this workshop is to provide the users of ASICs and the customers of chip developers with the needed knowledge in order to achieve fruitful cooperation with their design partners and thus achieve a successful chip development. For this purpose, an overview of all design phases of ASICs, such as specifications, modeling, simulation, layout and testing, is presented first. The necessary technical basics are explained with the right amount of relevant theory and demonstrations.
The other major focus of the workshop is on the correct management of the chip development process, especially the distribution of responsibility between customer and designer, as well as their respective obligations and rights. In order to aptly highlight the significance of important design management tools such as table of requirements, table of specifications, design freeze, this workshop incorporates real case studies as well as group activities. At the end of the workshop a complete design example will be carried out live.
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Location: TGU Polymath Analog an der TTI GmbH, Nobelstraße 15, Stuttgart
Time: 9.00 am to 5.00 pm
Costs: Per attendee EUR 1700,00 including VAT for companies, EUR 1200,00 for universities, research institutes and individuals